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-- IP VLNV: xilinx.com:ip:ace5lite_traffic_gen:1.0
-- IP Revision: 1

-- The following code must appear in the VHDL architecture header.

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT axi_tg_pl_master_to_ddr
  PORT (
    s_axi_aclk : IN STD_LOGIC;
    s_axi_aresetn : IN STD_LOGIC;
    core_ext_start : IN STD_LOGIC;
    m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    m_axi_awaddr : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
    m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    cmdram_unused : OUT STD_LOGIC_VECTOR(83 DOWNTO 0);
    m_axi_awakeup : OUT STD_LOGIC;
    m_axi_awvalidchk : OUT STD_LOGIC;
    m_axi_awidchk : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_awaddrchk : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_awlenchk : OUT STD_LOGIC;
    m_axi_awctlchk0 : OUT STD_LOGIC;
    m_axi_awctlchk1 : OUT STD_LOGIC;
    m_axi_awctlchk2 : OUT STD_LOGIC;
    m_axi_awuserchk : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_awakeupchk : OUT STD_LOGIC;
    m_axi_awsnoop : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_awdomain : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_awstashniden : OUT STD_LOGIC;
    m_axi_awstashnidchk : OUT STD_LOGIC;
    m_axi_awstashnid : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
    m_axi_awstashlpiden : OUT STD_LOGIC;
    m_axi_awstashlpidchk : OUT STD_LOGIC;
    m_axi_awstashlpid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
    m_axi_awuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axi_awvalid : OUT STD_LOGIC;
    m_axi_awready : IN STD_LOGIC;
    m_axi_wlast : OUT STD_LOGIC;
    m_axi_wlastchk : OUT STD_LOGIC;
    m_axi_wdata : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
    m_axi_wdatachk : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_wstrb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    m_axi_wstrbchk : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    m_axi_wvalid : OUT STD_LOGIC;
    m_axi_wvalidchk : OUT STD_LOGIC;
    m_axi_wready : IN STD_LOGIC;
    m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_bvalid : IN STD_LOGIC;
    m_axi_bready : OUT STD_LOGIC;
    m_axi_breadychk : OUT STD_LOGIC;
    m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    m_axi_araddr : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
    m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_arvalidchk : OUT STD_LOGIC;
    m_axi_aridchk : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_araddrchk : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_arlenchk : OUT STD_LOGIC;
    m_axi_arctlchk0 : OUT STD_LOGIC;
    m_axi_arctlchk1 : OUT STD_LOGIC;
    m_axi_arctlchk2 : OUT STD_LOGIC;
    m_axi_aruserchk : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_arsnoop : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_ardomain : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_aruser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axi_arvalid : OUT STD_LOGIC;
    m_axi_arready : IN STD_LOGIC;
    m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    m_axi_rlast : IN STD_LOGIC;
    m_axi_rdata : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
    m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_rvalid : IN STD_LOGIC;
    m_axi_rready : OUT STD_LOGIC;
    m_axi_rreadychk : OUT STD_LOGIC;
    irq_out : OUT STD_LOGIC 
  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : axi_tg_pl_master_to_ddr
  PORT MAP (
    s_axi_aclk => s_axi_aclk,
    s_axi_aresetn => s_axi_aresetn,
    core_ext_start => core_ext_start,
    m_axi_awid => m_axi_awid,
    m_axi_awaddr => m_axi_awaddr,
    m_axi_awlen => m_axi_awlen,
    m_axi_awsize => m_axi_awsize,
    m_axi_awburst => m_axi_awburst,
    m_axi_awlock => m_axi_awlock,
    m_axi_awcache => m_axi_awcache,
    m_axi_awprot => m_axi_awprot,
    m_axi_awqos => m_axi_awqos,
    cmdram_unused => cmdram_unused,
    m_axi_awakeup => m_axi_awakeup,
    m_axi_awvalidchk => m_axi_awvalidchk,
    m_axi_awidchk => m_axi_awidchk,
    m_axi_awaddrchk => m_axi_awaddrchk,
    m_axi_awlenchk => m_axi_awlenchk,
    m_axi_awctlchk0 => m_axi_awctlchk0,
    m_axi_awctlchk1 => m_axi_awctlchk1,
    m_axi_awctlchk2 => m_axi_awctlchk2,
    m_axi_awuserchk => m_axi_awuserchk,
    m_axi_awakeupchk => m_axi_awakeupchk,
    m_axi_awsnoop => m_axi_awsnoop,
    m_axi_awdomain => m_axi_awdomain,
    m_axi_awstashniden => m_axi_awstashniden,
    m_axi_awstashnidchk => m_axi_awstashnidchk,
    m_axi_awstashnid => m_axi_awstashnid,
    m_axi_awstashlpiden => m_axi_awstashlpiden,
    m_axi_awstashlpidchk => m_axi_awstashlpidchk,
    m_axi_awstashlpid => m_axi_awstashlpid,
    m_axi_awuser => m_axi_awuser,
    m_axi_awvalid => m_axi_awvalid,
    m_axi_awready => m_axi_awready,
    m_axi_wlast => m_axi_wlast,
    m_axi_wlastchk => m_axi_wlastchk,
    m_axi_wdata => m_axi_wdata,
    m_axi_wdatachk => m_axi_wdatachk,
    m_axi_wstrb => m_axi_wstrb,
    m_axi_wstrbchk => m_axi_wstrbchk,
    m_axi_wvalid => m_axi_wvalid,
    m_axi_wvalidchk => m_axi_wvalidchk,
    m_axi_wready => m_axi_wready,
    m_axi_bid => m_axi_bid,
    m_axi_bresp => m_axi_bresp,
    m_axi_bvalid => m_axi_bvalid,
    m_axi_bready => m_axi_bready,
    m_axi_breadychk => m_axi_breadychk,
    m_axi_arid => m_axi_arid,
    m_axi_araddr => m_axi_araddr,
    m_axi_arlen => m_axi_arlen,
    m_axi_arsize => m_axi_arsize,
    m_axi_arburst => m_axi_arburst,
    m_axi_arlock => m_axi_arlock,
    m_axi_arcache => m_axi_arcache,
    m_axi_arprot => m_axi_arprot,
    m_axi_arqos => m_axi_arqos,
    m_axi_arvalidchk => m_axi_arvalidchk,
    m_axi_aridchk => m_axi_aridchk,
    m_axi_araddrchk => m_axi_araddrchk,
    m_axi_arlenchk => m_axi_arlenchk,
    m_axi_arctlchk0 => m_axi_arctlchk0,
    m_axi_arctlchk1 => m_axi_arctlchk1,
    m_axi_arctlchk2 => m_axi_arctlchk2,
    m_axi_aruserchk => m_axi_aruserchk,
    m_axi_arsnoop => m_axi_arsnoop,
    m_axi_ardomain => m_axi_ardomain,
    m_axi_aruser => m_axi_aruser,
    m_axi_arvalid => m_axi_arvalid,
    m_axi_arready => m_axi_arready,
    m_axi_rid => m_axi_rid,
    m_axi_rlast => m_axi_rlast,
    m_axi_rdata => m_axi_rdata,
    m_axi_rresp => m_axi_rresp,
    m_axi_rvalid => m_axi_rvalid,
    m_axi_rready => m_axi_rready,
    m_axi_rreadychk => m_axi_rreadychk,
    irq_out => irq_out
  );
-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file axi_tg_pl_master_to_ddr.vhd when simulating
-- the core, axi_tg_pl_master_to_ddr. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.



